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 F-RAM Technology and Products |
| F-RAM Parallel Memory |
Q: What are parallel F-RAM devices?
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A: Standard asynchronous SRAMs have been available in the market for many years. The interface is the simplest, and it is the type of memory that most designers think of when referring to “RAM.” It has a few control pins (/CE, /WE, /OE), an address bus, and a data bus. Ramtron offers x8 and x16 parallel parts. |
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Q: Why use a parallel F-RAM?
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A: Today, Ramtron offers x8 (bytewide) and x16 (wordwide) memory devices. Traditionally SRAMs have been used in systems that use a x8 memory. Speed is an advantage of a parallel memory device over serial parts. All address lines are presented at once and an access can start immediately. Data is transferred into and out of the memory 8- or 16-bits at a time. |
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Q: Does /CE need to toggle for every access?
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A: No, the new FM28V100 and FM28V020 devices as well as the FM21L16, FM22L16/22LD16, and FM23MLD16 have on-chip ATD circuits which allow the memory to access any location by simply changing the address. This feature is called Address Transition Detection and allows /CE to remain low. It is true that the FM1608 and FM1808 devices require /CE to toggle.
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| F-RAM Processor Companion |
Q: Why doesn’t the RTC/oscillator run? Why is the RTC running slow? It seems that I have everything connected properly on my board, however I cannot activate the RTC with the crystal.
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A: Check that your board layout is clean - do not route switching signals next to the X1/X2 pins and be sure to have a guard-ring around the X1/X2 pins. Typically if the crystal pins are being disturbed by nearby switching signals, you will observe the CAL output is much lower than 512 Hz. Other things to check: be sure to remove solder flux near crystal pins, replace the crystal, initialize all battery-backed registers to a value within its valid range. |
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Q: What is the Ibak current when I insert a battery and Vdd is off?
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A: When a battery is first attached to the FM31xx while Vdd is powered off, there are a number of registers inside the chip that come up in an unknown state. These circuits are connected to the internal power supply. It is possible that the Ibak current is a few microamps or as much as 100 microamps. It's a random startup condition. Once Vdd is applied, the Ibak current goes to zero. All internal circuits are set to known states. When Vdd is then powered down, the Ibak current is < 1uA. This issue has been resolved on the FM3127x, FM31L27x, FM33xx, FM3130, and FM3135 devices. |
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Q: How long will a backup supercap last after a power loss?
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A: Using a 1F supercap, the RTC will operate for approximately two weeks. |
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Q: How much time will it take to charge up a supercap?
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A: A: The FM3130, FM3135, FM3127x, FM31L27x, and FM33xx have a fast charge mode. If a 1F supercap has been discharged to 1.5V, it will take approximately 30 minutes.
See also: AN404 – RTC Backup and UL
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| F-RAM Serial Memory |
Q: What are serial F-RAM devices?
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A: For many systems that are cost sensitive or space-constrained, it is important to design with physically small ICs and/or few chip-to-chip wires. Two-wire (I2C) and SPI devices satisfy these needs. The two-wire protocol that uses clock and data, was developed by NXP/Philips in the 1970s and is still very prevalent today. SPI devices are known as a three-wire interface, /CS, clock, and data, however “data” is comprised of two pins. A data input and data output. Most systems that use SPI devices have a four-wire interface. SPI devices operate at a higher clock frequency and therefore offer higher data rates. |
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Q: Why use I2C over SPI, or vice versa?
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A: Two-wire (I2C) is the most common and many micros implement a two-wire dedicated port. SPI operates at much higher clock rates, up to 20MHz. For simplicity and the use of fewer I/O micro pins, two-wire is generally used. |
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Q: How do I tell which density F-RAM device I have without looking at the part marking?
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A: You can write a known value (such as FF) to addresses 00h, 800h, and 2000h, then write data 11h to address 800h and do a read to address 00h. If you read 11h, then you know it is a 16Kb part. If you read FFh, then you can continue to the next boundary. Write data 22h to address 2000h and read address 00h. If you read 22h, then you know it is a 64Kb part. If you read FF, then it is a 256Kb device. You can apply this scheme to both I2C and SPI families. |
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| General F-RAM Product FAQs |
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| General F-RAM Technology FAQs |
Q:
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A: Please see the F-RAM technology timeline on our History page. |
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Q:
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A: F-RAM is commercially proven in the semiconductor market with over 300-million units sold. In addition, F-RAM uses much less power while operating and cannot be affected by external magnetic fields.
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Q:
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A: Ramtron has formed strategic product licensing and/or manufacturing alliances with several large firms including Texas Instruments, Fujitsu, Toshiba, Samsung, Hitachi, NEC, Rohm and Samsung. Currently Fujitsu, is our primary foundry and we recently announced a manufacturing agreement with Texas Instruments for high-density F-RAM products.
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Q: What is F-RAM?
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A: F-RAM is a nonvolatile memory device that can hold data even after it is powered off. F-RAM is an acronym for ferroelectric random access memory. F-RAM is not ferromagnetic as there is no ferrous material (iron) in the chip. Ferroelectric materials switch polarity in an electric field, but are not affected by magnetic fields.
See also: Ferroelectric Technology Brief and What is F-RAM.
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Q: Are F-RAM devices affected by magnetic fields?
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A: F-RAM devices are ferroelectric memories and are not ferro-magnetic. They are not affected by external magnetic fields.
See also: F-RAM Technology Brief
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Q: Is FeRAM the same as F-RAM?
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A: Yes. FeRAM and F-RAM are synonymous. Ramtron does not hold a trademark on the word “F-RAM”. It may be freely used without restriction. |
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Q: What are the key advantages over EEPROM and Flash?
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A: 1) Speed. The “RAM” part of the F-RAM name tells us that it is a RAM, not a ROM. Of course, EEPROM and Flash are not truly ROMs but writing to them can be very slow. An F-RAM’s write cycles are completed immediately whereas an EEPROM/flash needs 5 to 10 ms.
2) Low Power Writes. Writes to the F-RAM cell occur at low voltage and very little current is needed to change the data. With EEPROM and Flash, high voltages (10V charge pump) are needed and writes require 5 ms to complete a page buffer write. The energy needed is much higher than F-RAM writes. If E=P*t, then 5ms of write time will necessarily require 200x more energy than F-RAM.
3) High Endurance. Writes are destructive – and floating gate devices eventually wear out; typical endurance is 100,000 to 1 million cycles. F-RAM experiences 1E12 read/write cycles or greater.
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Q: How large of an electric field can a F-RAM device withstand?
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A: The F-RAM memory cell operates by applying a switched voltage to sense and restore the data state. The ferroelectric film PZT is about 2000 A (0.2 um) thick. If the device is placed in a 50 kV field at 1 cm, it is not possible to produce more than 1V across the ferroelectric film. As a practical matter, F-RAM devices are impervious to external electric fields. |
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Q: Is F-RAM affected by radiation or soft errors?
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A: Volatile memories, DRAM and SRAM, use a capacitor to store charge or a simple latch to store state. These cells can be easily upset by a alpha particles, cosmic rays, heavy ions, gamma, x-rays, etc. which cause bits to flip to an opposite state. This is called a soft error, since a subsequent write will be retained. The rate at which this occurs is called the Soft Error Rate (SER) of the device. Because the F-RAM cell stores the state as a PZT film polarization, an alpha hit is very unlikely to cause the polarization to change a given cell’s state. The F-RAM terrestrial SER is not measurable. |
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| I2C Interface |
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| SPI Interface |
Q: Why can’t I get SPI writes to work?
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A: You must issue a WREN opcode before the WRITE opcode. The WREN opcode requires the /CS pin to go low, clock-in the opcode (06h), then /CS must return high. The WRITE opcode then follows. The /CS pin goes low, clock-in the opcode (02h), clock-in the address (up to 3 bytes depending on the density), clock-in the data (1 or more bytes), then /CS must return high.
See also: AN304 SPI Guide.
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| Wireless Memory/RFID |
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| Support |
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| Versa 8051 MCUs |
| I²C Interface |
Q: Can the I²C interface operate in slave mode?
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A: Yes, the VRS51L2070/3xxx can operate in both master and slave mode. It is also possible to configure the I²C device ID. |
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Q: How fast can the I²C interface communicate?
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A: The I²C interface can communicate up to Fosc/32. When the VRS51L2070/3xxx operates from the 40MHz internal oscillator, the I²C interface can run up to 1.25Mbps. |
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Q: Is the I²C speed adjustable?
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A: Yes. Communication speed on the I²C interface is controlled by an 8-bit register. This provides a wide adjustment range, enabling the user to optimize the I²C communication speed to specific I²C bus characteristics, such as length or number of devices connected to it. A longer I²C bus requires a lower communication speed. For example, if the VRS51L2070/3xxx operates from the 40MHz internal oscillator, the I²C interface communication speed is adjustable from 4.8KHz to 1.25MHz. |
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| Flash and SRAM Memory |
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| F-RAM (VRS51L3xxx) |
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| General Information |
Q: What is special about the VRS512070/3xxx compared to other high performance MCUs?
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A: VRS51L2070 and VRS51L3xxx devices meet the current market demand for a high performance MCU, without a costly investment in new architecture and code. They have the power and speed to compete with a 16-bit MCU without migrating from an 8-bit device; they are compatible with the 8051-based architecture, code and development environment; and they have a comprehensive set of highly configurable digital peripherals that enables full integration and eases the load on the processor. |
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| I/O and Driving Capability |
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| Internal Oscillator |
Q: Can both the internal and the crystal oscillators run simultaneously?
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A: Yes, but only one oscillator can be used to supply the system clock at a time. By default, upon a system reset the VRS51L2070/3xxx starts from the internal 40MHz oscillator. If the application requires operation from an external crystal, the program will need to activate the crystal oscillator, wait enough time for the crystal oscillator frequency to stabilize, and then switch the system clock source to the crystal oscillator. At that point, the internal oscillator can be deactivated. |
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Q: Can I use the UART serial ports when the VRS51L2070/3xxx operates from the internal oscillator?
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A: Yes, the internal oscillator provides sufficient precision and stability for this. To compensate for the fact that 40MHz is not a multiple of standard RS-232 communication frequencies, each UART includes a 16-bit baud rate generator with a 4-bit micro baud rate adjustment feature. |
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Q: How precise is the internal oscillator?
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A: The internal oscillator is calibrated to 40MHz +/- 300 kHz. |
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Q: What is an internal oscillator?
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A: The internal oscillator is a VCO circuit calibrated to oscillate at 40MHz. An onboard internal oscillator renders an external crystal unnecessary and minimizes system costs. The VRS51L2070/3xxx can also operate from an external crystal oscillator if need be. |
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| Interrupts |
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| JTAG Interface |
Q: Is there a USB version of the Versa JTAG interface available?
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A: Yes. |
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Q: What is the purpose of the JTAG interface?
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A: The JTAG interface on the VRS51L2070/3xxx is a 4-pin interface (TDI, TDO, TMS, CM0), which enables in-circuit Flash memory programming and real-time in-circuit debugging of the VRS51L2070/3xxx. It can also be used for circuit boundary scan verifications. |
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Q: What is the purpose of the JTAG interface?
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A: The JTAG interface on the VRS51L2070/3xxx is a 4-pin interface (TDI, TDO, TMS, CM0), which enables in-circuit Flash memory programming and real-time in-circuit debugging of the VRS51L2070/3xxx. It can also be used for circuit boundary scan verifications. The interface connects to the PC parallel port and ships with the VersaKit-20xx/30xx development system for the VRS51L2070/3xxx.
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| Mac + Div Unit |
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| Packaging |
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| Power and Supply |
Q: What is the operating voltage range of the VRS51L2070/3xxx?
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A: The VRS51L2070/3xxx operates from 3.0V to 3.6 volts. |
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Q: How can power consumption on the VRS51L2070/3xxx be minimized?
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- If the VRS51L2070/3xxx is running from the internal 40MHz oscillator, use the clock control module to reduce the frequency of the system clock propagated to the processor core and peripherals.
- If using an external crystal oscillator, set the lowest crystal frequency possible and use the clock control module to reduce the frequency of the system clock propagated to the processor core and peripherals.
- For interrupt-based applications, lower the system clock between interrupts.
- Disable unused peripherals and set the prescaler value to its maximum.
- Run from a lower frequency external crystal oscillator.
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Q: What is the power consumption on these devices?
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A: Power consumption on the VRS51L2070/3xxx depends on which peripherals are active. Typically, when the device operates from the 40MHz internal oscillator, power consumption ranges from 17mA to 27mA. If the clock control module is set to reduce the system clock to 10MHz, power consumption goes down to about 7.5mA. |
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| Processor |
Q: Can the VRS51L2070/3074 processor run from the SRAM memory?
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A: Yes. Program code can be moved to the 4KB block of SRAM memory so that the processor runs from that location. Please note that when the processor is running from the SRAM, variables cannot be declared in that area. |
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Q: Does code developed on a standard 8051 run directly on the VRS51L2070/3xxx?
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A: Yes and no. The VRS51L2070/3xxx uses the same internal memory architecture and processor-related registers (i.e. accumulator, DPTR, B register etc.) as standard 8051 devices. Code developed on a standard 8051 that does not access peripherals will run on the VRS51L2070/3xxx (i.e. I/Os, timers, UARTs, communication interfaces, etc.).
The peripherals’ SFR register structure on the VRS51L2070/3xxx differs from that on a standard 8051. Therefore, functions that require internal computation and data processing can be ported directly onto the VRS51L2070/3xxx, while functions accessing peripherals require an adjustment in order to run on the VRS51L2070/3xxx.
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Q: How much faster is the VRS51L2070/3xxx processor compared to a standard 8051 MCU?
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A: Substantially faster: Depending on the benchmark used to compare devices, the difference ranges from about 8 to 12 times faster. For instance, since the VRS51L2070/3xxx does not include a x12 clock divisor between the oscillator and the system clock, theoretically, the VRS51L2070/3xxx is 12 times faster than industry standard 8051 MCUs.
In a recent study conducted by Ramtron, we compared the processing power of the VRS51L2070/3xxx vs. a standard 8051 while executing 16-tap FIR filtering calculations. The VRS51L2070/3xxx performed about 8 times faster than the standard 8051.
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Q: What is the maximum operating speed of the VRS51L2070/3xxx processor?
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A: The VRS51L2070/3xxx processor can run up to 40MHz. Since oscillator cycles directly translate into processor cycles, program instructions are treated at a speed of up to 40 MIPS depending on the instruction length. |
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Q: What kind of processor does the VRS51L2070/3xxx feature?
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A: The VRS51L2070/3xxx is based on a single-cycle 8051 processor. Unique to many 8051-based MCUs on the market, there is no clock divider between the oscillator and the processor, enabling tremendous performance gain over standard 8051 MCUs. |
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| Pulse Width Counter |
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| Pulse Width Modulators |
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| Software and Programming |
Q: When the Versa-JTAG USB programmer is connected to the VersaKit-30xx development board, I can program the Flash memory and run the program. However, if I disconnect the Versa-JTAG programmer and do a power cycle, the program does not start. What is wrong?
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A: This behavior can be explained by the state of the VRS51L3xxx CM0 pin at power-on reset.
To operate the VRS51L3xxx in stand-alone mode, the jumper on JP7-CM0 must be removed and a power cycle must be performed.
The VRS51L3xxx's CM0 pin, which is sampled at power-on reset, controls the operating mode of the chip:
- When CM0 pin = 1 (or pin is disconnected) the device starts in Run Mode. In Run Mode, the JTAG is deactivated and the processor starts after a power-on reset.
- When CM0 pin = 0 (jumper installed on JP7-CM0) the VRS51L3xxx will start in Programmer Mode. In Programmer Mode, the JTAG interface is activated and the processor is halted, awaiting JTAG commands.
To use the Versa JTAG-USB interface, the jumper on JP7-CM0 must be installed. To start the processor after programming during a debug session or when the “run” button is activated, the Versa Ware JTAG software sends a “Program Run” command to the device through the JTAG interface.
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Q: Which compilers are recommended for use with the VRS51L2070/3xxx?
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A: Almost any 8051 C compiler/assembler can be used to develop code for the Ramtron MCUs. The following compilers are recommended to develop code for the VRS51L3xxx because they are supported by the Versa Ware JTAG debugger:
- SDCC freeware C compiler
- Keil
- Ride-51
SDCC is a command line tool and requires a text editor. Most demo programs for the VRS51L2070/3xxx were compiled with SDCC.
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Q: Which development tools exist for the VRS51L3xxx?
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A: The VersaKit-30xx is a plug-and-play evaluation and development kit for the VRS51L3xxx that ships complete with development board, USB-JTAG programming/debugging interface and required software and documentation.
See MCU Software Support Tools Downloads
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Q: Which software should I use to program the VRS51L2070/3xxx?
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A: Versa Ware JTAG is software developed by Ramtron for JTAG-based MCUs like the VRS51L2070, the VRS51L3xxx and future derivatives.
Versa Ware JTAG provides the programming interface and executes real time in-circuit debugging. For device programming, the Versa Ware JTAG software is compatible with standard the Hex file format, while in-circuit debugging supports SDCC, Keil and RIDE compiler output file formats.
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| SPI Interface |
Q: Can the SPI interface operate in slave mode?
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A: Yes. |
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Q: How quickly can the SPI interface run?
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A: The maximum communication speed on the SPI interface is Fosc/2. This corresponds to 20Mbps when the device operates from the internal 40MHz oscillator. |
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Q: What is special about the SPI interface on the VRS51L2070/3xxx?
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A: One of the unique features of the SPI interface is that its transaction size is adjustable from 1 to 32 bits. Transactions over 32 bits, in multiples of 8, are possible with careful interrupt management.
The SPI also allows automatic control of the chip select (CS) lines. This eliminates the need for the user program to bring the I/O connected to the CS line low before the SPI transaction begins and bring it back up when the transaction is complete. The SPI interface also provides a CS manual mode that will keep the CS line low when a transaction is complete.
With these features, the SPI is the ideal high-speed interface for A/D & D/A converters, F-RAM memory devices, DSP host systems, etc.
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| UART Serial Ports |
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